Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
The programming used to configure an FPGA or other PLD is often very complex. It is common to use a modeling system to simulate the operation of the programming to evaluate how a physical FPGA will operate when used in a system, such as a system on a chip (“SoC”). In some systems, a PLD interfaces with or includes functional blocks. For example, an FPGA includes an embedded processor operating at a first clock speed, and an I/O interfacing peripheral and a customized computation peripheral (such as a digital processing or image processing filter) operating at a different clock speed. Multiple simulators are integrated into the modeling system to simulate the different functional blocks. In yet other instances, the PLD devices themselves are used in the simulation as emulators. In this case, a portion of a design physically runs on a PLD device while the rest of the design is simulated by the simulators running on a host PC. A modeling system interface controls the simulation progress of the software simulators or emulation hardware, and exchanges simulation data between them when needed.
System level design requires the ability to quickly connect and adapt compatible blocks together. Previously, this required that block interfaces either match by design or be explicitly designed to match a known standard by the development team(s). The former approach restricts the set of usable blocks to only those provided by a system level design tool, while the latter approach requires cumbersome re-design work when legacy designs are upgraded or changed.
Capturing the behavior and properties of block interfaces in IC systems has been studied in depth for quite some time. Previous work has focused on capturing interface timing and behavior through a variety of methods including waveforms or automata descriptions (e.g., state machines). Using automata to define interface behavior between blocks is widely used because almost any sequence of signal assertions can be described. Numerous algorithms have been devised to resolve differences in interface automata leading to the synthesis of a bridging component between two disparate interfaces. However, the limitations of these approaches lie in the inability to capture and resolve all aspects of interface differences, particularly in pipelined operations, data width mismatches, or clock domain differences. In addition, a thorough state machine description, though general, is often too cumbersome to use in describing an interface of a user block. The time and effort required to write an interface automata for a user block may not be that far off from designing a bridging element directly, thus offering no benefit for quick system-level prototyping.
Techniques for comparing and resolving inter-block connections in an IC system that avoid the disadvantages of the prior art are desirable.